FIG. 8 illustrates outlines of a TOF-MS using a data acquisition circuit studied by the inventors as a premise of the present invention.
The TOF-MS is an apparatus in which a sample is ionized and accelerated in a space and a time of flight in the space, which depends on its mass, is measured, thereby analyzing components contained in the sample. The sample is ionized in an interface 1, and is then reached to a Time-of-Flight (TOF) region 2.
The ion fed to the TOF region 2 is accelerated at a timing of a pulse signal 11a generated from a pulser 11. The accelerated ion flies through the course represented by an arrow in the drawing inside the TOF region 2, and then reaches (collides with) a detector (micro channel plate) 21, thereby generating a detection signal 2a. A gain adjuster 4 connected to a stage previous to the data acquisition circuit 5 adjusts the amplitude of the detection signal 2a, and a detection signal 4a after the amplitude adjustment is inputted to the data acquisition circuit 5.
In the data acquisition circuit 5, the time of flight of the ion is repeatedly measured with this detection signal 4a, and acquired addition data (measurement results) 5b is outputted to a user interface unit 62 via a CPU 61.
Here, systems of acquiring time-of-flight data in the data acquisition circuit 5 include a Time to Digital Converter (TDC) system and an Analog to Digital Converter (ADC) system. In the apparatus for quantitative analysis of each component contained in the sample, the ADC system is often used.
The amplitudes of the detection signal 2a are different in accordance with the number of ions reaching (colliding with) the detector (Micro Channel Plate) 21. In the TDC system, a time and the number of detections are acquired when the data exceeds a certain level (threshold level) regardless of the magnitude of the amplitude of the detection signal 2a. Meanwhile, in the ADC system, the amplitude data is acquired at predetermined time intervals.
The gain adjuster 4 connected to the stage previous to the data acquisition circuit 5 adjusts the amplitude of the detection signal 2a, and then the detection signal 4a after the amplitude adjustment is inputted to an A/D converter 51 of the data acquisition circuit 5. The detection signal 4a after the A/D converter 51 at the timing of a reference converts the amplitude adjustment clock 50a generated by a clock generator 50 into digital data 51a representing a voltage value, and the digital data 51a is stored in a signal intensity addition memory 53. FIG. 9 shows an example thereof. Subsequently, after a measurement is repeatedly performed up to the number of times set by a user, the addition data is transferred to the CPU 61, and data analysis is performed in the CPU 61. However, since the next measurement cannot start during data transfer, all of the data transfer time corresponds to a measurement suspension time.
FIG. 10 illustrates one example of a procedure in the above-described ADC system. In this example, in a process 1, a measurement and an addition computation are performed 100 times. In a process 2, all pieces of data stored in the process 1 are transferred to the CPU 61. Also, it is assumed that each measurement time is 1 ms, a sampling speed of the A/D converter 51 is 1 Gsps, a bus speed at the time of CPU transfer is 25 MHz/point, and an address region of the signal intensity addition memory 53 is 1 mega (M) points. In this example, a time required for the process 1 is 100 ms (=1 ms×100 times), and a time for the process 2 is 40 ms (=1 M points/25 MHz).
Here, since the next measurement (process 1) cannot start during the data transfer, all of the time of the process 2 corresponds to a measurement suspension time. In this example, approximately 40% of the measurement time is a measurement suspension time, which leads to a degradation in measurement efficiency.
Also, in the above-described ADC system, since it is required that n-bit sampling data from the A/D converter 51 representing the amplitude of the detection signal is obtained on the order of M points and further the obtained data is subjected to an addition process, the entire amount of data is increased in comparison with the TDC system. For the solution of this problem, for example, Japanese Patent Application Laid-open Publication No. 11-287807 discloses the technology of removing unnecessary sampling data, and United States Patent Application Publication No. 2003-0173514 discloses a data compression process such as the noise reduction by means of threshold levels.
In FIG. 11, as a technology associated with United States Patent Application Publication No. 2003-0173514, a data compression (noise reduction) technology studied by the inventors as a premise of the present invention is depicted.
Sampling data from an A/D converter includes not only a peak spectrum but also a lot of unnecessary data such as a noise level, for example. Therefore, in this data compression technology, a threshold level is set and the sampling data equal to or lower than the threshold level is cut off without being written in the memory, and only data exceeding the threshold level is transferred.
There are a variety of schemes for processing the data at the points which are cut off because the data is equal to or lower than the threshold level, which include an offset operation system in which data equal to or lower than a predetermined level (in the drawing, the threshold level) is offset uniformly to the threshold level as shown in FIG. 11A and a threshold level operation system in which all pieces of data equal to or lower than a predetermined level (threshold level) are treated as 0 level as shown in FIG. 11B.
In these data compression processes, when data compression is performed to the addition data, since it is required that all pieces of measurement data are transferred to the CPU and then a compression process is performed by the CPU, a problem of increasing a measurement suspension time (data transfer time) occurs.
Moreover, in the technologies discussed in the above-mentioned Japanese Patent Application Laid-Open Publication No. 11-287807 and United States Patent Application Publication No. 2003-0173514, processor processing or hardware multiplexing is performed. Therefore, a problem that the process becomes complicated and the cost is increased occurs.